##  [Latch‑Up](/latch-0) 

 Definition

A low‑impedance, self‑sustaining conduction state in CMOS integrated circuits produced by activation of parasitic p‑n‑p and n‑p‑n transistor pairs (a parasitic thyristor or SCR) that creates a current path between supply rails; it is triggered by injection of charge or overvoltage and persists until the current is removed or limited, potentially causing thermal damage or device failure.

 

 

 

 

 

 





## Principle

Principle

The CMOS process geometry creates adjacent p‑ and n‑doped regions that form parasitic complementary transistor pairs; when these parasitic transistors become forward‑biased they provide positive feedback that latches the circuit into a conductive SCR‑like state — prevention relies on layout (guard rings, well ties), doping and process choices, and current limiting rather than solely transient filtering.

 

 

 

 

 





## Demonstration

Demonstration

Illustrative scenario — Situation: an input pin of a bulk CMOS device experiences an ESD pulse that injects charge into the substrate. Recognition: supply current rises dramatically and remains high while functionality stops. Action: power is removed or a current limiter trips. Consequence: if current persists, localized heating may damage junctions or metallization; with proper layout and substrate ties the transient is shunted and latch‑up avoided.

 

 

 

 

## Misapplication

Misapplication

Confusing latch‑up with non‑destructive transient upset (e.g., single‑event upset) or assuming that presence of ESD protection diodes alone eliminates latch‑up risk; the semantic error is failing to recognize that latch‑up is a sustained parasitic SCR conduction requiring substrate and well considerations and current management.

 

 

 

 

 





## Consequence

Consequence

Undetected latch‑up can lead to catastrophic device failure, thermal runaway and system-level faults; addressing latch‑up affects process selection, die layout, I/O protection design and system current‑limiting strategies, and can impose tradeoffs with performance or area.

 

 

 

 

## Reversal

Reversal

Semiconductor technologies that isolate devices from substrate (e.g., silicon‑on‑insulator, SOI) or that use deep wells and heavily tied substrates greatly reduce or largely eliminate latch‑up susceptibility; additionally, designs that include robust current limiting can allow a latch event to be non‑destructive though functionality is still interrupted.

 

 

 

 

 





## Boundary

Boundary

Clearly within: bulk CMOS devices where parasitic pnp and npn structures can form an internal thyristor between VDD and VSS. Boundary case: partially isolated wells with some substrate ties — latch‑up risk reduced but dependent on layout and transient severity. Clearly outside: discrete circuits explicitly built as thyristors or well‑isolated SOI devices where the parasitic SCR path is absent or negligible.

 

 

 

 

 





## Semantic Tension

Semantic Tension

Density/Performance Versus Robustness — aggressive scaling and high‑density layouts improve performance and density but can exacerbate latch‑up susceptibility unless compensated by process isolation or layout practices, creating a tradeoff between miniaturization and latch‑up immunity.

 

 

 

 

 





## Synthesis

Synthesis

Latch‑up is a parasitic, positive‑feedback conduction mode inherent to certain device structures; effective mitigation requires coordinated choices across process, layout and system protection rather than relying on a single protective element.