A transient, non‑destructive change of logic state in a digital memory cell or logic element caused by a single energetic particle (charged ion, proton, neutron or secondary ionization) depositing sufficient charge to exceed the node's critical charge; the physical device structure remains functional unless other damage occurs.

Principle

An SEU occurs when charge deposited at a sensitive node produces a voltage perturbation that crosses the cell's switching threshold; vulnerability scales with node capacitance, supply voltage, layout geometry and incident particle linear energy transfer (LET).

Demonstration

Illustrative scenario (hypothetical): A satellite's SRAM cell is struck by a cosmic heavy ion, depositing charge that flips one bit. Onboard error‑correcting code (ECC) detects a single‑bit error during a read and corrects it; a subsequent scrub clears the corrupted copy from configuration memory, preventing system-level misbehavior.

Misapplication

Treating SEU as permanent physical damage. This error conflates a transient logic‑state upset with destructive single‑event effects; SEU is a state change that is typically corrected by overwrite, ECC, redundancy or reset, not repaired by replacing silicon.

Consequence

Unmitigated SEUs can propagate to higher‑level faults (software errors, corrupted packets, incorrect control commands). Mitigation options (ECC, redundancy, remote scrubbing, hardened cell designs) trade area, power and latency against system reliability. Testing and qualification must target the relevant operating environment and bit‑cell types.

Reversal

If the upset occurs in nonvolatile configuration or memory that is not overwritten (e.g., unprotected flash/fuse/EEPROM), the upset can become persistent; additionally, simultaneous multiple adjacent SEUs (multi‑bit upsets) or secondary events (e.g., SEL) can convert a nominally transient SEU into a lasting failure.

Boundary

Clearly within: a single bit in SRAM flips value after a particle strike but the cell's transistor network is intact. Boundary case: multiple adjacent bit flips in a memory word (MBU) that exceed ECC capability. Clearly outside: parametric degradation from total ionizing dose (TID) or physical, thermally‑induced metallization failure.

Semantic Tension

Design trade‑off between device density/performance (reduced node charge, lower voltage) which increases SEU susceptibility, and the system‑level cost/complexity of mitigation (ECC, redundancy, hardened processes).

Synthesis

SEU is a charge‑injection driven, logic‑level transient: understanding it requires both device‑level sensitivity (critical charge) and system‑level protection strategies because the technical solution space spans materials, cell design and architecture.