An empirical observation from the semiconductor industry that transistor counts on integrated circuits have historically increased roughly exponentially over successive technology generations, often correlating with improvements in cost‑adjusted computing capability; it is an industry heuristic rather than a physical law.

Principle

Regular increases in transistor density tend to reduce cost per function and enable higher performance or greater integration, but this trend depends on technological, economic and physical constraints and so may change in pace or character over time.

Demonstration

Illustrative scenario → Situation: A fabrication node shrinks enabling twice the transistors per die. Recognition: Designers can add more functional units or reduce cost per transistor. Action: A processor redesign leverages higher density for parallel units and cache. Consequence: For given cost, system throughput or feature integration increases, though single-thread performance gains may be limited by other factors.

Misapplication

Assuming Moore's Law guarantees indefinite, uniform increases in single‑thread performance or that transistor count directly translates to proportional application speed; the error is conflating transistor density with unlimited or linear performance scaling.

Consequence

Moore's Law has guided industry roadmaps, investment and system architecture choices; when scaling slows, industry adapts via heterogeneous computing, specialized accelerators, packaging advances and software optimization.

Reversal

When physical scaling (lithography, thermal limits, quantum effects) or economic cost structures prevent further density gains at historical rates, the historical pace and character of improvement no longer apply and emphasis shifts to architectural, software, or packaging innovations.

Boundary

Clearly within: transistor count and on‑die integration on semiconductor ICs. Boundary case: performance improvements achieved by architecture, compiler or algorithmic advances rather than raw transistor scaling. Clearly outside: claims about general technological progress unrelated to semiconductor scaling.

Semantic Tension

Expectation of continuous exponential hardware scaling ↔ Physical and economic limits that force alternative engineering tradeoffs.

Synthesis

Moore's Law functions as an engineering and economic roadmap: it predicts a practical cadence of capability improvement that drives design and investment decisions, but it is contingent on technological and economic feasibility rather than an immutable physical principle.